A low dead time variable CMOS delay for the Nuclear Weapons Identification System

The architecture and performance of a new CMOS, low dead time, variable delay is described. This delay was developed to provide channel synchronization in the front-end electronics ASIC of the Nuclear Weapons Identification System (NWIS). The delay is variable over a 500 ns range in steps of less than 100 ps. Low dead time is achieved by using a switched parallel channel architecture. The delay channels are feedback stabilized by using a phase locked loop with a crystal reference. A prototype has been fabricated in the 1.2 /spl mu/m AMI process.