On the performance and limitations of a dual threshold discriminator pixel readout circuit for LHC

The analog frontend of pixel readout electronics with dual threshold discriminator scheme has been measured extensively to determine the conditions for optimum performance as well as the circuits performance limitations. The preamplifier shows a peaking time of 20 ns without capacitive load, which degrades to only 30 ns with a load of 350 fE The LEVEL-discriminator has an adjustable threshold in the range of 2000 to 6000 e/sup -/ with a variable separation to the TIME-discriminator threshold of 800 to 1600e/sup -/. The circuit allows the full suppression of out-of-time signals under the conditions of 350 fF capacitive load and a total power consumption of 40 /spl mu/W per cell. The untuned threshold dispersion is measured to be 320 e/sup -/ r.m.s., which reduces to 70 e/sup -/ r.m.s, after threshold adjust. The overall noise of the circuit reaches a value of about 200 e/sup -/ r.m.s. With 350 fF capacitive load and 20 nA of parallel current at the preamplifier input. Further measurements characterize the time-over-threshold (TOT) behaviour and the double-pulse resolution of the circuit.