A disturbance-aware sub-block design to improve reliability of 3D MLC flash memory

The reliability problem of modern flash-memory chips quickly deteriorates because of the nature of MLC chips. Although the vertical stacking of storage cells in 3D flash-memory chips dramatically increases the bit density, compared to 2D chips, it also results in severe disturbance problems. In this work, we propose to create sub-blocks in the MTD layer by considering different program disturb resistance patterns, without any hardware cost. In particular, a disturbance-aware sub-block design is proposed to utilize the hotness information of data to further improve the reliability of 3D MLC flash memory by smartly choosing sub-blocks to use when extra information is available from the flash translation layer. The proposed design was evaluated by a series of experiments over traces from SNIA. It was shown that the disturb errors could be reduced by at least 50% under DFTL and BL, i.e., a page-level FTL and a block-level FTL design, compared to the conventional MLC programming designs.