A low power EEPROM for passive RFID tag IC

EEPROM is widely used in RFID passive tags and the power consumption restricts the reading distance to readers. In this paper, a novel structure of EEPROM is proposed to investigate the potential power reduction. From the analytical results of distribution on power dissipation of the conventional EEPROM, the charge pump and the sense amplifier take the most part. A novel cascaded structure of charge pump is applied to decrease the power consumption at 23.4% with grouping the units and modifying the frequency of input clock. Moreover, the active capacitance load is also r educed by inserting idle duty cycle. Then again, an improved sense amplifier with selective control gates is presented and the SA will share the bandgap with the charge pump. The power dissipation of SA is achieved at 370 µW. This proposed 8k-byte EEPROM is designed and fabricated in SMIC 0.18µm 2P6M process and the chip area is 0.93×0.93 mm
²
. The measurement results from the test chip are demonstrated and compared with the conventional structure.