Low-voltage high-gain folded architecture operational amplifier

This paper describes the design and results of a low-voltage high-gain CMOS operational amplifier (op-amp) which is very appropriate for low-voltage analog and mixed-signal applications. The design is based on folded architecture. The amplifier was designed using standard 180 nm digital n-well CMOS technology to operate with a 1.8 V single supply. The simulated small-signal AC gain of the amplifier is 90.79 dB and slew rate is 11.5 V/us with a 10 pF capacitive and 1 M ohm resistive load. For the same load, the gain bandwidth is 14.23 MHz with a phase margin of 54.8 degree. The amplifier consumes total DC power of 167 uW. The input-referred noise is 110 nV/sqrt(Hz). Furthermore, the presented operational amplifier works perfectly at supply voltage of 1 V.