Neural processor design enabled by memristor technology

Matrix-vector multiplication is a key computing operation in neural processor design and hence greatly affects the execution efficiency. Memristor crossbar is highly attractive for the implementation of matrix-vector multiplication for its analog storage states, high integration density, and built-in parallel execution. The current deign schemes can be generally divided into two different approaches - “spiking-based” design and “levelbased” design. The performance and robustness of the proposed neural process designs are also evaluated by using the application of digital image recognition. In this work, a heuristic flow including device modeling, circuit design, architecture, and algorithm is studied. The proposed neural processor designs that leverages nano-scale memristor technology are summarize and compared. This work indicates that the spiking neuromorphic engine has a good tolerance in resistive device imperfection, but more vulnerable to the fluctuations in output spike generation. The improved level-based computing engine has a higher computation accuracy with better stability.