Security improvement of FPGA configuration file against the reverse engineering attack

FPGAs are widely used platforms in many of secure applications. Field-programmability of FPGAs is an effective feature in the growth and diversity of their applications but it has caused security concerns for IPs/Designs on FPGAs. Bitstream is a binary file which is generated at the end of the last stage of FPGA design flow. Unfortunately, there is a straightforward and quite relationship between the bitstream and design knowledge. This matter is considered as a security disadvantage in reverse engineering attack. In this paper we analyze this vulnerability and provide a solution to complicate the coding of the bitstream to hinder reverse engineering of FPGAs. In our proposed solution, the architecture of the bitstream encoding is changed and some select pins are added to the multiplexers inside the switch boxes. This modification causes a new coding method for bitstream. In this way the existing peer-to-peer relationship between the design and its bitstream would be disturbed. The experimental results show that with a negligible overhead, this coding method is able to improve the obfuscation level of the bitstream and hamper the reverse engineering attack.