Ground plane influence on zero-temperature-coefficient in SOI UTBB MOSFETs with different silicon film thicknesses

This paper presents an analysis of the Ground Plane (GP) influence on the Zero Temperature Coefficient (ZTC) in Ultra Thin Body and Buried Oxide (UTBB) Silicon On Insulator (SOI) nMOS transistors for different silicon thicknesses (t
_Si
) based on experimental data and analytical models. The presence of a GP increases the values of the bias voltage of ZTC (V
_ZTC
) due to the reduction of the substrate effects in the device and consequently the increase of threshold voltage. The VZTC shows to be inversely proportional to the silicon thickness. All results are confirmed by the analytical model for the threshold voltage, which is the predominant factor in the ZTC point for this technology, both showing the same tendency.