Implementation of crossbar switch for NOC on FPGA

Now-a-days every electronics system, ranging from small mobile phone to satellite has SOC (System-on-chip). Over the years, SOC has undergone rapid evolution and are still processing at a swift pace. But due to this explosive evolution of semiconductor industry, the devices are scaling down at a rapid rate and hence, SOC today have become communication-centric. However the existing bus architectures comprising of wires for global interconnection in SOC design are undergoing design crises as they are not able to keep up with the rate of scaling down of devices. In response to this crises, NOC (network-on-chip)is an upcoming archetype and is becoming a leading contender to replace conventional bus architectures. Many NOC topologies have been introduced in an attempt to tackle various chip architecture needs and routing technique. The mesh topology is well suited for incorporating regular size processing elements on single chip. It is also quite simpler to design and incorporate various routing protocols into it as opposed to others. Thus to validate the functioning of NOC on hardware, crossbar architecture has been designed in VHDL and simulated in Xilinx ISE 14.1 targeting Xilinx XC5VLX30-3 FPGA.