Low power & high performance implementation of multiplier architectures

In this work, a new technique known as bypass technique has been introduced mainly to reduce the switching power dissipation. In array multipliers, this technique offers huge dynamic power saving but due to their regular interconnection scheme, it misses the reduced area and high speed advantages of tree multipliers. Hence we have introduced a mixed architecture style which contains a tree multiplier and a carry save multiplier with bypass technique ensures high performance also. The implementation has been carried out on Virtex4 FPGA. The power values are obtained from Xpower Analyzer and the results shows the significant reduction in power when tested at different frequencies.