A Novel Gate-Stack-Engineered Nanowire FET for Scaling to the Sub-10-nm Regime

In this paper, we propose a novel dual-metal gate-stack (DMSG) architecture with HfO2 spacer for scaling the nanowire FETs (NWFETs) to the sub-10-nm regime. We demonstrate that the electric field at the channel-drain extension interface is reduced when the inbuilt electric field arising due to a difference in the work function at the interface of the two metals in the DMSG is coupled to the nanowire through the fringing fields through the HfO
₂
spacer. The reduction in the electric field leads to a larger tunneling width, and therefore suppresses the lateral band-to-band-tunneling component of the gate-induced drain leakage in the DMSG NWFETs. Although the gate capacitance increases in the DMSG NWFETs due to the fringing fields, this paper demonstrates that the increase in the intrinsic delay (~1.5 times) is not very significant to degrade the circuit performance drastically. Using calibrated 3-D simulations, we show that the off-state current is reduced by more than five orders of magnitude in the DMSG NWFETs, leading to a significantly high on-state to off-state current ratio of ~10
⁶
even when the channel length is scaled to 7 nm.