A high speed KDL-RAM file system for parallel computers

The design, implementation, and performance of a main memory file system are presented. The implementation is based on a two-stage abstract parallel processing model. The objective of this model is to maximize throughput and minimize response time. To maximize throughput, lock structures, access structures, and shared variables are distributed among the shared memories. A novel approach based on hash-based parallel accesses is used. The effect of lock conflict is minimized by an optimistic locking protocol. Analytical models are developed for hot spot memory accesses, distributed data accesses, and space-versus-time tradeoffs for fast accesses to records. On the basis of the performance results of these models, a high-speed KDL-RAM (key accessed, dynamically reconfigurable, distributed locked random-access memory) file system has been implemented on the Butterfly PLUS Parallel Processor. Various performance results of this system are given. It is shown that the performance improvement of this system is considerably better than BBN's Butterfly RAMFile system on the Butterfly PLUS Parallel Processor.<
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