A new recursive algorithm for multidimensional convolution

This paper presents a novel recursive algorithm for generating higher order m-dimensional (m-D) convolution by combining the computation of 3/sup m/ identical lower order (smaller size) convolution computations, and its implementation in parallel VLSI networks. The resulting VLSI architectures have very simple modular structure, highly regular topology, and use simple arithmetic units. Additionally, the proposed architectures have very small depth and contain only a single stage of multipliers, while all other stages contain adders only.