Sigma-delta ADC with reduced sample rate multibit quantizer

Based on the well-known Leslie-Singh architecture, a new cascaded sigma-delta analog-to-digital conversion (ADC) architecture is proposed. It incorporates a multibit quantizer whose sample rate can be significantly lower than the full oversampling speed of the sigma-delta modulator. Simulation results and comparison with other architectures are given. The architecture can be a good choice to extend the use of sigma-delta ADC to high bandwidth applications.