A low voltage CMOS square law analog multiplier

A multiplier composed of a low voltage square-law CMOS cell is introduced in this paper. The analysis of the square-law cell is given. The multiplier operates in the saturation region with a fully balanced input signal. Initial simulations were done for 0.8 /spl mu/m n-well process using BSIM3 model parameters. The circuit has a trade-off between low voltage operation and low power dissipation. The circuit has a cutoff frequency of 99.4 MHz and P/sub dis/=1.5 mW for a bias current of 120 /spl mu/A. The THD is less then -51 dB and -49 dB for fixed input voltages V3 and V1, respectively, for a 1 MHz, 0.5 V peak-to-peak sinusoidal input.