Fault model for VLSI circuits reliability assessment

A new fault model, based on the general percolation theory applied to long-channel CMOS VLSI circuits, has been recently introduced. It was shown that a reliability risk appears only when process-related defects create a pattern independent current path in standby mode. An acceptable reliability risk defines a pass/fail criteria. A screening technique, based on this model, presents a strong correlation between rejected devices and early failure rate. In this paper, the general percolation approach was applied to short-channel CMOS VLSI circuits. Unlike long-channel CMOS VLSI, defect-free short-channel CMOS VLSI circuits inherently have a pattern independent standby current, which results from a short-channel MOSFET current in the off state. In this case, the defect related component of this current may be released only by means of a multi-parameter failure criterion. Experimental results that confirm this conclusion are presented and discussed. The reliability risk assessment technique employing this model shows a strong correlation between rejected devices and long term reliability for 32-bit 0.35 /spl mu/m CMOS microprocessors.