Impact of BTBT, stress and interface charge on optimum Ge in SiGe pMOS for low power applications

The feasibility of medium-high fraction SiGe based FinFET pMOS devices for a sub-10nm CMOS logic technology from a performance (I
EFF
@ fixed I
OFF
) standpoint is evaluated, considering three key device aspects — stress, band-to-band-tunneling (BTBT), and interface charge density (DIT). The analysis reveals that while for high Ge (>90%), performance is limited by BTBT, overall stress reduction beyond Ge 65% further limits performance. Including realistic (DIT) profile further shows that optimum Ge content is between 40%∼50% for low power applications.