Physical modeling of ferroelectric field-effect transistors in the negative capacitance regime

Field-effect transistors (FETs) with a ferroelectric insulator instead of a conventional gate dielectric have been shown to operate in a negative capacitance (NC) regime when properly engineered, giving rise to a less than 60 mV/decade subthreshold slope (SS) at room temperature. In this paper a comprehensive, physics-based model for the investigation of such ferroelectric FETs (FeFETs) is reported. Contrary to standard semi-analytical and 0-D approaches it relies on a multi-dimensional description of the simulation domain, thus offering the possibility not only to study the characteristics of gate stacks, but also the overall scalability of FeFETs. As key finding it is revealed here that the presence of large electric fields on the drain side of transistors tends to suppress the NC effect, which becomes an issue in short channel devices.