Process informed accurate compact modelling of 14-nm FinFET variability and application to statistical 6T-SRAM simulations

This paper presents a TCAD based design technology co-optimization (DTCO) process for 14nm SOI FinFET based SRAM, which employs an enhanced variability-aware compact modeling approach that fully takes process and lithography simulations and their impact on 6T-SRAM layout into account. Realistic double patterned gates and fins and their impacts are taken into account in the development of the variability-aware compact model. Finally, global process induced variability and local statistical variability and their impacts are evaluated at the transistor and SRAM levels.