Atomistic simulation flow for source-drain epitaxy and contact formation processes of advanced logic devices

An atomistic simulation flow for contact formation process was developed and integrated into logic transistor frontend process simulation. Existing atomistic kinetic lattice Monte Carlo model of epitaxy process was extended to silicidation. Metal and silicon diffusion and silicide formation reactions were taken into account at atomic level which allowed accurate simulation of silicide shape including faceting effects. This approach enables device performance prediction depending on design rules and parameters thus providing a way for TCAD-based technology optimization. As an implementation example a contact resistance prediciton depending on contact opening and recess depth for a 10-nm class logic device is demonstrated.