A possible explanation of the record electrical performance of silicon nanowire tunnel FETs with silicided source contact

Some experimentally implemented silicon nanowire tunnel FETs with silicided source contacts show an unexpectedly high electrical performance. Simulations using state-of-the-art simulation models and assuming usual device geometries cannot explain the high performance of these transistors: Conventional simulations of such tunnel FETs predict an on-state current which is several orders of magnitude lower than measured. In this work we show that thin silicide nano-spikes extending from the silicided source contact into the silicon channel of the nanowire tunnel FET could be a possible explanation of the high tunnel FET performance observed experimentally.