A fully-synthesizable 0.6V digital LDO with dual-loop control using digital standard cells

A fully synthesizable digital low drop-out regulator (LDO) with dual (coarse/fine) loops control is proposed. This structure employs a synchronized comparator to compare the feedback voltage (Vfb) and the desired reference voltage (Vref). A coarse loop is used to simplify the control logic circuit and increase the LDO response speed during the output dynamic transit. A fine loop is used to minimize the output ripple voltage of the LDO in the steady-state. A dynamic detection circuit using dual offset comparators is employed to detect the output voltage variation. To minimize the current consumption, the switching frequency is scaled to 1/32 of original frequency in steady-state. The circuit is implemented by purely digital standard cells. Simulation results at 130nm CMOS technology shows that this structure can achieve a peak current efficiency of 99.9% using a 1 MHz clock and a 0.6 V supply.