Novel info wafer-level-chip-scale-package N-leak test and stress

This paper introduces a manufacturing process screening methodology for Integrated Fan Out Wafer Level Chip Scale Packaging (InFO WLCSP) which has the promise of being a very cost effective solution to achieve "More than Moore's law" for mobile devices - more so than 3D integrated circuits (3DIC). InFO WLCSP has several test challenges due to new defect modes that have never been faced before. Previous test methods take long test time and often have poor test performance. In this paper we propose test solutions that lead to a short test time and a higher test coverage for yield learning. We will demonstrate the methodology in some industrial cases to validate our claims.