A 6.25% Pull-in Range Digital PLL for ISDN Primary Rate Interface LSI

This paper describes a digital PLL which can realize both wide pull-in range and small output jitter by adopting a self controlled free running frequency. This characteristic is suitable for LSI because the wide pull-in range does not require highly accurate clock and on-chip oscillator can be used. As the result, the expensive external components such as crystals can be eliminated and fully integrated digital PLL is obtained. Circuits are designed for the ISDN primary rate interface LSI. and CCITT I.431 specification are satisfied.