Complementary III–V heterostructure tunnel FETs

In the present work we will show our complementary TFET technology, which allows for the co-planar integration of InAs/Si p-TFETs and InAs/GaSb n-TFETs. We demonstrate both types of devices, show the results of the electrical characterization at room temperature and down to 125K. The p-TFETs exhibit excellent performance with I
_on
of a couple of μA/μm (|V
_GS
| = |V
_DS
| = 0.5V) combined with average subthreshold swing, SS, of 70-80mV/dec. The all III-V n-TFETs show about an order of magnitude higher I
_on
, but their SS is limited by the non-optimized gate stack and doping profiles. Thorough simulation studies of our devices show trap-assisted tunneling at the heterojunction to be the main limitation on SS. We will discuss the impact of different trap mechanisms and compare our results with other experimental data.