A 12b 180MS/s 0.068mm2 pipelined-SAR ADC with merged-residue DAC for noise reduction

This paper presents a 12b 180 MS/s partial-interleaving Pipelined-SAR analog-to-digital converter (ADC). The 1
^st
-stage is implemented with a 2b/cycle SAR ADC for high speed, where we propose a merged-residue-DAC technique to improve the noise performance. The capacitor pre-charging in conventional 2b/cycle operation wastes settling time and switching energy, while with this design approach the switching procedure is optimized to avoid the pre-charging for tri-level reference generation. The prototype ADC fabricated in 65nm CMOS achieves a SNDR of 63.8dB @DC input with 6mW power dissipation from a 1.2V supply, leading to a FoM @DC of 26.3 fJ/conv.-step.