The design of delay insensitive asynchronous 16-bit microprocessor

Recently, asynchronous design has resurged to exploit potential advantages of asynchronous VLSI such as; high-performance, low power consumption, timing fault tolerance and design cost reduction. This paper describes our first design and implementation of the DINAMIK project which aims to show realizability of potential merits of asynchronous VLSI and to establish the design methodology. In the design, ease of design (high modularity) and delay insensitivity were especially emphasized while power consumption, performance and area optimization were ignored as the first stage of the project. To achieve our main purpose, a simple architecture and a pessimistic delay assumption have been selected. DINAMIK has been fabricated using 0.6 /spl mu/m CMOS technology.