A VLSI switch architecture for broadband satellite networks

In this paper, an ATM switch architecture is proposed for satellite on-board processing. The switch is based on a shared memory architecture for the switching fabric and a circular sorting queue for the buffer management unit. The design is constrained by both the network performance requirements and the limited payload of the satellite in terms of mass, area and power. A low-power ASIC implementation of the sorting queue that can support an aggregate traffic rate up to 21.2 Gbps is also presented.