A 1 Gb/s CMOS clock and data recovery circuit

So far, high-speed CMOS clock and data recovery (CDR) circuits usually use a multi-phase oversampling technique that has limited acquisition range and requires a reference clock. The Gb/s CMOS CDR in this paper does not need any reference clock input. The CDR achieves a wide acquisition range of /spl plusmn/200 MHz and small RMS jitter of 7.4 ps (0.0074 UI) in the recovered 1 GHz clock.