A 500 MHz pipelined burst SRAM with improved SER immunity

One of the components key to increased mobile computer performance is level-2 (L2) cache memory, which is usually a high-frequency synchronous SRAM and typically consumes >2 W. This SRAM has to be housed in low-thermal-resistance package such as the plastic ball grid array (PBGA). Power dissipation must be reduced, since battery life is prolonged and a lower-cost TQFP package can be used. In addition, cosmic-ray-induced single soft errors are becoming a problem, since memory cell node capacitance is reduced with reduction of memory cell size. At high altitude (air flight level of 30000 ft), cosmic-ray-induced SER is increased by 2 orders of magnitude. This type of soft error is significant for mobile applications. The 64k x 36 synchronous pipelined burst SRAM (PBSRAM) described has lower power and improved SER immunity.