A novel noise margin model of surrounding-gate MOSFET working on subthreshold CMOS logic gates

In this paper, we present a novel noise margin model of surrounding-gate MOSFET working on subthreshold CMOS logic gates. Based on the device physics and equivalent transistor model, theoretical analysis of noise margin for SRG MOSFET operating in low-voltage condition is revealed. It is shown that the device parameters such as the thick silicon thickness t_si, thick gate oxide thickness t_ox, short channel length L_g, and low supply voltage V_dd can severely degrade the noise margin NM. On the contrary, the small subthreshold slope induced by device parameters can suppress the NM degradation efficiently. Being similar to DIBL, NM degraded by the device parameters can also be uniquely determined and controlled by the scaling factor according to scaling theory.