SOM hardware with acceleration module for graphical representation of the learning process

A digital hardware implementation of self-organizing maps is presented. Dedicated hardware is implemented that allows the on-line visualization of the map during learning. The use of a scalable parallel architecture enables the realization of large scale high performance maps. Fist silicon was produced in a 0.8 /spl mu/m, 2 metal layer CMOS technology, implementing about 161,800 transistors on a die size of 28.58 mm/sup 2/. Experimental results are presented, that prove the functionality of the design up to a clock frequency of 40 MHz. A classification rate of 250,000 vectors per second and an adaptation rate of 94,000 vectors per second can be guaranteed, independent from the size of the network.