Augmenting pre-silicon simulation by embedding a scripting language in a SystemC environment

Advancements in manufacturing technologies allow to integrate an ever increasing amount of functionality into single System on Chip devices (SoCs). This not only causes the well-known productivity gap, it also challenges the proper verification of these designs. While the efficiency of pre-silicon verification of purely digital designs is continuously increased, either by the use of sophisticated Hardware Verification Languages (HVLs) or with powerful software suites, there is a lack of applicable concepts for mixed-signal designs. Furthermore, pre- and post-silicon verification activities are still often treated separately preventing to exploit possible synergies. For these reasons there is a great need for new innovative mixed-signal verification methods and flows that are able to cope with a soaring amount of functionality further aggravated by a shrinking time-to-market. This paper presents an approach to use abstract test descriptions written in Perl (1) to increase the efficiency of the verification process of complex mixed-signal SoCs designs in a SystemC simulation environment and (2) to enable information exchange between pre- and post-silicon activities. Since Perl and SystemC are distinct languages several approaches to link them together were elaborated and are presented in this paper. Their suitability with respect to several key aspects is compared and their effectiveness for pre-silicon verification is evaluated on the basis of an example test case.