A new current mode high speed four quadrant CMOS analog multiplier

In this paper current mode analog CMOS multipliers are shortly reviewed and categorized. Then a new current mode four-quadrant analog multiplier circuit is proposed. The new circuit structure is based on trans-linear loops and employs three new compact squaring circuits. Simpler circuit structure, lower power dissipation, lower THD and higher bandwidth are some advantages of the proposed multiplier and also the input resistance is independent of the input current. Post layout simulation results of the multiplier using Cadence Spectre and Asura in 0.18μm standard CMOS technology shows a THD of 1.01% (@1MHz), a −3dB bandwidth of 840 MHz, and a power consumption of 89.2 μW.