Dual-loop enhanced-gain fast-response CMFB for open-loop RAs in high-resolution ADCs

A novel common mode feedback, CMFB, mechanism is proposed with concurrent use of high and low gain loops. High-Gain loop slowly corrects the absolute CM level of the RA's outputs. Also, the low-gain loop is speed up to compensate the fast fluctuations on output CM level. Gain of the slow-response loop is enhanced using the magnified variations on drain-source voltage of NMOS devices in response to small overdrive voltage variations when the bias current is constant. In the proposed high-gain CMFB loop, both the main operations, detecting the output CM voltage level and applying the loop response to the main RA, are performed via the virtual ground nodes. The proposed CMFB loop adjusts the CM voltage level of the RA to the absolute value of 2Volts within the error range of less than ±1.5mVolts when the loop gain is enhanced to around 75dB. The single-pole liked settling behavior in presence of 1pF load capacitance reliably guarantees the stability features. THD of differential outputs experiments 5dB-to-8dB improvement in some corners in compare to the conventional structures. High-Gain loop consumes less than 660μW at 3.3Volts supply voltage in a 0.18μm CMOS process.