A 288-μW 6-GHz hybrid dynamic comparator with 54-ps delay in 40-nm CMOS

This paper presents an energy-efficient high-speed hybrid dynamic comparator with reduced delay in 40-nm CMOS process. The first dynamic amplifying stage uses PMOS input to reduce the common-mode voltage, thus the required minimum supply voltage, while enhancing the positive feedback to reduce the discharge time in a low-power manner. The second quasi-dynamic latching stage uses NMOS input to gain the transconductance, thus reducing the latch delay with negligible static power, while needing no additional clock signal. Simulation results show that the proposed comparator operates up to 6 GHz with 54-ps delay, while consuming only 288 μW at 1.1-V supply.