Investigation on the defect induced thermal mechanical stress for TSV

Through Silicon Via (TSV) technology is a promising and preferred way to realize the reliable interconnection for 3D IC integration. TSV based 3D IC packaging mainly consists of via formation, via filling, wafer thinning and chip stacking. Copper is one of the most commonly used materials for via filling which is a significant process and challenge in TSV manufacturing processes. However, defects introduced during copper filling process would induce some reliability problems. In this paper, a numerical model of Cu-filled TSV was established to simulate and analyze the effect of defects for TSV thermal mechanical stress. Specifically, the defects in the shape of circle, square and triangle were built in the TSV model, respectively. Then, the effect of defects with different shape on thermal stress distribution were investigated. Moreover, the impact of the size and location of the defect on thermal stress was also studied. Simulation results show that thermal stress distribution in TSV is distinct with the different shape and location of defect. Additionally, the maximum equivalent stress of the TSV with triangular or square defect increases as the increase of the size of defect.