Implementation of configurable linear feedback shift register in VHDL

This paper focus on the implementation of configurable linear feedback shift register (CLFSR) in VHDL and evaluates its performance with respect to logic, speed and memory requirement in FPGA. Behavioral implementation of CLFSR in VHDL is configurable in terms of number of bits in the LFSR, the number of taps, positions of each tap in the shift register stage and seed value of LFSR. The target device used for implementation of CLFSR is Xilinx Virtex-4 FPGA. For simulation and synthesis of CLFSR Xilinx ISE 9.2i tool is used. The output waveforms and timing report are also discussed.