A 5-GS/s, 13-mW, 2-channel time-interleaved asynchronous ADC in 65nm CMOS

This paper presents a high-speed energy-efficient analog-to-digital converter (ADC) with two-channel time-interleaving on an asynchronous pipelined-flash architecture for each channel. With use of multiple sampling paths as well as asynchronous control by a low-power 6-phase clock generation, the proposed ADC eliminates power-hungry and bandwidth-limited residue amplifiers without sacrificing the speed. The ADC prototype is fabricated in 65-nm CMOS process with measured power consumption of 13 mW and speed of 5-GS/s with 37dB SFDR and 30dB SNR in 2.5GHz bandwidth.