Vertical versus lateral tunneling FET non-volatile memory cell

This work reports a comparison of high-k Al
₂
O
₃
/HfO
₂
/Al
₂
O
₃
dielectric stack Tunnel FETs with both vertical tunneling and lateral tunneling, as non-volatile memory (NVM) cells. Tunnel FET NVM are fabricated and characterized to evaluate their potential as low power memory operation. These memory cells can be programmed with voltages from -10V to -15V (p type devices) and show extremely stable memory hysteresis up 400K with very low leakage. We experimentally show that, in strong contrast with conventional lateral tunneling TFET, the vertical tunneling TFET based NVM memory has a much higher memory window (V
_T
shift) due to excellently aligned gate field and tunneling path in the latter case.