A Probabilistic Framework for Compiler Optimization with Multithread Power-Gating Controls

Various studies have attempted to reduce the leakage power using integrated architectures and compiler-based power-gating mechanisms. These approaches involve compilers inserting instructions into programs to shut down and wake up components as appropriate based on a compiler data-flow analysis. When applying the power gating control in compilers for multithreading programs, conventional methods can not be applied directly due to that the threads might share the same hardware resources. This paper presents a multithread power-gating framework composed of a multithread power-gating power model and a probabilistic time-slice based multithread power-gating algorithm for reducing the leakage energy when executing multithread programs on simultaneous multithreading (SMT) machines. Our framework estimates the energy usage of multithread as power controls for energy management. Compared to previous work, our method applies power control in multithread programs to the whole program of a concurrent thread region while the previous work only considers the head and tail of a concurrent region. We performed experiments by incorporating our power optimization framework into SUIF compiler tools and by simulating the energy consumption with a SMT simulator based on Wattch toolkits. The experimental results shows about 10% energy reduction in random generated graphs of multithread programs relative to one without power-gating, where leakage contribution was set to 30%. In OpenCL-based BSP kernels, our method reduces total energy by average of 35% that demonstrates our method is efficient on reducing leakage energy of multithread programs in SMT environment.