Nanoscale evidence for the superior reliability of SiGe high-k pMOSFETs

It is commonly accepted that the susceptibility of conventional Si channel pMOSFETs to the negative bias temperature instability (NBTI) is a serious threat to further scaling. One possible solution of this problem is the use of SiGe quantum-well devices, which not only offer high mobilities but also superior NBTI reliability compared to conventional silicon transistors. It has been speculated that the latter is due to the energetically higher valence band edge of the SiGe channel with respect to Si, which increases the energetic separation between the defect bands in the high-k gate stack and the channel. We investigate this claim by comparing the behavior of single-defects in nanoscale devices to the averaged behavior of the large number of defects visible in large-area devices. Using detailed TCAD simulations together with the four-state non-radiative multiphonon model we determine the energetic and spatial locations of the traps in the gate stack and confirm that the previously developed picture correctly explains the significant reliability benefits of SiGe channel devices.