BTI induced dispersion: Challenges and opportunities for SRAM bit cell optimization

One of major CMOS reliability concern for advanced nodes is the Bias Temperature Instability mechanism. In addition to the native local process dispersion, BTI induced dispersion is becoming a field of intensive research. Important works focus on the distribution tail of the Vth shift after NBTI stress and efforts are deployed to high-sigma accurate modeling (defect-centric, Skellam). However, in many analog applications (ADC, SRAM) sensitive to devices matching, it is important to understand how the initial Vth distribution evolves in time. In this paper some key results of spread induced by BTI are reviewed for 14nm and 28nm Fully Depleted SOI from STMicroelectronics. Analysis between initial Vth and aged Vth correlation is presented. Then, measurement of fresh and post HTOL memory V
_DDmin
is presented for different conditions of temperature and process centering. Then, a powerful algorithm of yield optimization is presented. It enables design centering and yield improvement (through devices sizing by moving the mean value and modifying the local process parameter impact on the performance spread) including ageing, under constraint of foot print.