FinFET SCR structure optimization for high-speed serial links ESD protection

An optimized SCR structure was proposed for high turn-on speed and low parasitic capacitance in FinFET CMOS process. Experimental results indicate that the proposed SCR structure delivers the best known results among the literatures (140mA/fF). By adopting the structure, ESD protection design for multi Gb/s transceiver can be simply realized.