SE performance of a Schmitt-trigger-based D-flip-flop design in a 16-nm bulk FinFET CMOS process

A hardened flip-flop (FF) design using Schmitt-trigger circuits for improved soft-error (SE) performance is presented. The Schmitt-trigger-based DFF (STDFF) design along with conventional DFF in a 16-nm bulk FinFET CMOS process were tested using alpha particles, heavy-ions, proton, and neutron. The STDFF design shows ~162× improvement in the alpha SE cross-section, up to ~30× improvement in heavy-ion SE cross-section, and ~5× improvement in both proton and neutron failure in time (FIT) rates compared with conventional DFF at nominal supply voltage and room temperature. STDFF also outperformed DFF for SE cross-section over frequency (up to 1.3 GHz) and temperature (up to 125 °C) ranges of interest.