Statistical variability in n-channel SOI FinFET in the presence of random discrete dopant

Among the source of variability, random discrete dopant (RDD) fluctuation is significant in current technology scaling nodes. Number and position of discrete dopants give a crucial impact on device's electrical characteristics. In this paper, a comprehensive full-scale 3D simulation study of nanoscale n-channel Source-on-Insulator (SOI) Fin-Type Field Effect Transistor (FinFET) with gate length, Lg=22nm is investigated. 3D “atomistic” simulations for discretely doped case with 50 discrete dopants are randomly positioned into the 3D channel region to explore the statistical variability behavior of the device. Comparison between high and low channel doping (N_ch) and difference fin height-to-width ratio (H_fin/W_fin) have been made. As a consequence, it affected the statistical variability of the threshold voltage (V_th), sub-threshold slope (SS), and drain induced barrier lowering (DIBL) in the n-channel SOI FinFET device. The mean and standard deviation of these devices are calculated to analyze the electrical characteristics variation. For both devices with low and high channel doping concentrations, greater fin height-to-width aspect ratio (H_fin/W_fin) can significantly suppress the electrical characteristics variation.