Complementary III–V heterojunction lateral NW Tunnel FET technology on Si

We demonstrate for the first time a technology which allows the monolithic integration of both p-type (InAs-Si) and n-type (InAs-GaSb) heterojunction Tunnel FETs (TFET) laterally on a Si substrate. The lateral heterojunction nanowire (NW) structures are implemented using top-down CMOS-compatible processes combined with Template-Assisted Selective Epitaxy (TASE) [1] of the III-V materials. Sub-40nm InAs-Si p-TFETs and InAs-GaSb n-TFETs have been fabricated and represent to the best of our knowledge the first lateral III-V heterostructure NW TFETs. The InAs-Si p-TFETs show excellent performance with average subthreshold swing, SS
_ave
, of ~70mV/dec. combined with an on-current, I
_on
, of 4μA/μm at V
_DS
= V
_GS
= -0.5V. The InAs-GaSb n-TFETs have about an order of magnitude higher I
_on
, but SS is deteriorated due to high interface traps density (D
_it
).