Design and analysis of class-E inverter with MOSFET nonlinear gate-to-drain and nonlinear drain-to-source capacitances

This paper presents analytical expressions of the class-E inverter to satisfy the class-E ZVS/ZDS conditions, taking into account the effects of the MOSFET nonlinear gate-to-drain and nonlinear drain-to-source parasitic capacitances. A design example is given along with the PSpice-simulation and experimental waveforms at 2.0 W output power and 4 MHz operating frequency. The waveforms obtained from the PSpice simulation and circuit experiment showed the quantitative agreements with the theoretical predictions, which verify the expressions given in this paper.