Analytical Model and Optimization for Variable Drift Region Width SOI LDMOS Device

In this paper, we propose an analytical model for the variable drift region width (VDRW) silicon-on-insulator lateral double-diffused MOS (SOI LDMOS) device. Using the proposed model, for example, the breakdown voltage 375 V of VDRW SOI LDMOS is obtained with a 18-μm drift region length, while the average value of the surface electric field can reach 20.8 V/μm. A 3-D device simulator, Sentaurus, is used to investigate the performance of the VDRW structure. By analyzing the simulation results and the analytical values, it is proven that the proposed model can effectively optimize the doping profile and accurately forecast the breakdown voltage.