100 MHz Bclock period jitter case study for a cabled server platform

This paper studies the period jitter of CPU Bclock on a multi-board cabled server platform. The channel output signal is computed with linear superposition method to reduce run time compared to the step response SPICE transient simulation. The average clock period as well as the standard deviation of ten thousand unit intervals (UIs) were calculated. Output Pj at the clock buffer or chip receiver (Rx) pin is directly extracted at the channel output for different cable and clock scenarios.